In modern memory devices, small dimension and high capacitance value per unit area of a capacitor are desirable characteristics for achieving high charge storage capacity. The capacitors are usually formed by at least two layers of a semiconducting material and one layer of a dielectric material. For instance, in a polysilicon capacitor which is widely used in DRAM (dynamic random access memory) applications, a thin oxide layer is used to form an oxide sandwich between two polysilicon layers to produce a high capacitance capacitor cell.
In memory devices such as DRAM, while the dimensions of the device are continuously been miniaturized, methods for reducing the chip real estate occupied by a capacitor become more important. One such method proposed by others encompassing a design of stacking a capacitor over the bit line on the surface of a silicon substrate. The stacked capacitor is formed by a layer of dielectric material such as silicon oxide or oxide-nitride-oxide sandwiched between two layers of polysilicon. The effective capacitance of a stacked cell is increased over that of a convention planar cell due to its increased surface area. A conventional method of fabricating a stacked capacitor for DRAM is shown in FIGS. 1-5.
As shown in FIG. 1, a transistor 10 is first formed on a surface of the silicon substrate 12. A shallow trench field oxide layer 14 is also formed in the surface of the silicon substrate 12. A silicon nitride etch-stop layer 16 is then blanket deposited on the surface. This is shown in FIG. 2. Shallow trench isolation can be suitably used in high density (e.g. 64 M or larger) memory devices since it provides simplified back-end operation such as packaging. This is in comparison to a bird's beak type LOCOS isolation which provides an uneven top surface (or uneven topography) on a memory device and leads to poor photolithographic results due to focusing difficulties. Shallow trench isolation can be etched in the silicon between neighboring devices. It allows the devices to be built much closer together without the problem of effective channel width control since a field implant is no longer needed. The width of a device can be well defined by surrounding trenches without additional processing steps for the field implant. A more planar surface on the device can also be obtained by the absence of formation of bird's beak. Based on the advantages of a tighter line definition and a greater planarity provided by the shallow trench isolation, the isolation is very suitable for applications in sub-half-micron semiconductor processes.
In the next step of fabrication, as shown in FIG. 3, an oxide layer 18, or a cell contact non-doped silicate glass (CCNSG), is blanket deposited on the IC device. The CCNSG layer 18 is then patterned, photomasked and etched to form a cell contact hole 22, as shown in FIG. 4. After the formation of the cell contact hole 22, a layer of polysilicon 24, a layer of dielectric material (such as silicon oxide or oxide-nitride-oxide) 26 are deposited. This is shown in FIG. 5. After the two layers are patterned and etched by conventional processes to define the capacitor cell, a polysilicon layer 28 is deposited and then patterned and etched to define the capacitor cell 30.
In this conventional method, even though the side-wall thickness of the capacitor cell 30 is increased by the addition of the CCNSG layer 18, the limiting factor for the increased capacitance of the cell is the height of the cell that can be allowed.
It is therefore an object of the present invention to provide a capacitor cell in a DRAM device that has improved capacitance without significantly increase the cell height.
It is another object of the present invention to provide a capacitor cell in a DRAM device having improved charge capacity that does not require the deposit of a thicker CCNSG layer to increase the side-wall thickness of the cell.
It is a further object of the present invention to provide a capacitor cell in a DRAM device that incorporates the deposition of a plurality of oxide layers in place of a single CCNSG layer while maintaining the total height of the cell.
It is still another object of the present invention to provide a capacitor cell in a DRAM device that has enhanced side-wall area by the incorporation of a plurality of oxide layers wherein each layer is deposited by a deposition technique different than that used for depositing its immediate adjacent layers.
It is yet another object of the present invention to provide a capacitor cell for a DRAM device that has enhanced side-wall area by the incorporation of a plurality of oxide layers wherein each alternating layer is deposited by a different technique selected from a thermal CVD technique and a plasma CVD technique.
It is still another object of the present invention to provide a capacitor cell in a DRAM device that has enhanced side-wall area by incorporating a plurality of oxide layers wherein each layer has a density that is different than its immediately adjacent layers.
It is still another further object of the present invention to provide a capacitor cell in a DRAM device that has enhanced side-wall area by incorporating a plurality of oxide layers which can be etched by an etchant having different etch selectivity for the different oxide layers.
It is yet another further object of the present invention to provide a capacitor cell in a DRAM device that has enhanced side-wall area by incorporating a plurality of oxide layers that produce a corrugated configuration in the side-wall after an etching process.
It is yet another further object of the present invention to provide a capacitor cell in a DRAM device that has enhanced side-wall area by incorporating a plurality of oxide layers wherein the layers are etched by an acid having an etch selectivity ratio of at least 1:2 for the different oxide layers.